Intel Corp.’s research teams on Saturday unveiled work that the company believes will help accelerate and shrink computing chips over the next ten years, with multiple technologies aimed at some of the chips. The parts are to be stacked on top of each other.
Intel’s Research Components Group presented the work in papers at an international conference to be held in San Francisco. The Silicon Valley company has been working to gain an edge in making the smallest, fastest chips in recent years, losing out to rivals such as Taiwan Semiconductor Manufacturing Co. and Samsung Electronics Co., Ltd.
While Intel CEO Pat Gelsinger has laid out business plans aimed at achieving that lead by 2025, research work unveiled on Saturday shows how Intel plans to compete beyond 2025.
One way Intel is packing more computing power into the chips is by stacking “tiles” or “chiplets” in three dimensions, rather than building the chips as one two-dimensional piece. Intel showed off work Saturday that could allow up to 10 times more connections between stacked tiles, meaning more complex tiles can be stacked on top of each other.
But perhaps the biggest advance shown Saturday was a research paper showing a way to stack transistors — the tiny switches that make up the most basic building box of chips by representing the 1s and 0s of digital logic — on top of each other. .
Intel believes the technology will increase the number of transistors that can be packed into a given area on a chip by 30% to 50%. Increasing the number of transistors is the main reason why chips have grown steadily over the past 50 years.
“By placing the devices directly on top of each other, we’re clearly saving field,” Paul Fischer, director and senior principal engineer at Intel’s Components Research Group, told Reuters in an interview. “We’re reducing the length of the interconnect and really saving energy.” , making it not only more cost-effective, but also better performance.”
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